1. Field of the Invention
The present invention relates generally to a method and apparatus for capturing high-bandwidth commands and addresses. More particularly, the present invention relates to an address FIFO (first-in first-out) procedure and apparatus for use with a data storage system such as dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). A FIFO circuit buffers incoming memory address commands until corresponding data arrives to smooth data transfer to memory. The invention also relates to a FIFO buffer system which maintains the write pointer at least one buffer ahead of the read pointer to enable loading of buffers while others are being unloaded.
2. State of the Art
Faster and smaller circuits are the focus of much advancement in semiconductor technology. To address the need for faster and smaller circuits, a group of integrated circuits can be on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits on the bus to share data which is transmitted at a high-speed. An example of such a high speed data system is described in U.S. Pat. No. 5,917,760 to Millar (Jun. 29, 1999), the disclosure of which is incorporated herein by reference. Millar describes a high-speed data system using a common bus and a memory subsystem commonly known as SyncLink dynamic random access memory (xe2x80x9cSLDRAMxe2x80x9d). By providing an appropriate number of memory devices and an efficient control system as used in SLDRAM, very high-speed data transmissions can be achieved. However, faster systems, such as SLDRAM, are now reaching transfer speeds where the memory circuits cannot process the data as fast as the common bus can supply it. More specifically, as data storage address commands arrive at a memory system, if the corresponding data has not arrived yet, the address commands must be stored in a data pipeline until the data arrives. This address command backlog prevents use of the data pipeline by other processes, including transmitting other data, until the data corresponding to the address command arrives. This inconsistency in address command and data arrival times can result in increased data errors and lost data, but most often slows the system by creating a xe2x80x9cbottleneckxe2x80x9d of address commands.
A pipeline may be divided into any number of stages during which portions of commands are processed and executed. However, in a case of a memory device, such as SLDRAM, the series of processes typically includes: 1) an input process of address data; 2) a decoding process of the address data; 3) a reading process of data from a cell; 4) a transfer process of the data to an output circuit; and 5) an output process of the data. An example of a pipeline system used with DRAM is provided in U.S. Pat. No. 5,978,884 to Yamaguchi et al. (Nov. 2, 1999), the disclosure of which is incorporated herein by reference.
One solution which has been used in memory pipeline systems to correct for the bottleneck problem is to repeat much of the logic circuits within each logic pipeline to accommodate multiple simultaneous commands. However, adding more redundant logic circuits to a system is counter to the desire to make the overall system smaller.
Many telecommunication devices include first-in first-out (FIFO) circuits which temporarily buffer data arriving at a bandwidth higher than the bandwidth of the receiving system. A FIFO circuit stores incoming data, in the order it arrives, in temporary buffers which are then sequentially read out and used by the telecommunication subsystem for which they were intended. The FIFO circuit can store the mass of data which arrives before it can be processed in a temporary storage, and read it at a manageable speed. For example, a high-bandwidth data signal can be received at any speed by a telecommunication device, stored in the FIFO buffer, and read out at the processing speed of the device.
One example of a FIFO circuit used in a telecommunication system includes U.S. Pat. No. 4,507,760 to Fraser (Mar. 26, 1985). Fraser discloses random access memory (RAM) organized to act as FIFO memory and a control circuit to implement queue management for incoming/outgoing data in a digital communication system. A read pointer addresses the execution in the RAM from where a word may be read. A write pointer addresses the location in the RAM where a word may be entered. A xe2x80x9clastxe2x80x9d pointer addresses the location in the RAM where the last word of a complete message is stored.
Another example of a FIFO circuit used in a data communications system is described in U.S. Pat. No. 5,519,701 to Colmant et al. (May 21, 1996). Colmant et al. disclose a system to manage storage of data in FIFO circuits as data is transferred, in either direction, between the host bus and the network. By a queue manager allocating the queues which have the most activity, the queue manager can improve the speed of the transferring data while reducing the amount of bandwidth that would otherwise be required.
It is desirable to have a memory system which can handle the increased speed demands made by faster circuits, preserve data which arrives faster than the memory circuits can handle it, and do so without the redundancy of circuits required by existing memory systems.
The present invention addresses the problem of the bottleneck created in high bandwidth to smaller bandwidth systems through the use of a first-in first-out (FIFO) buffer system. The FIFO buffer system of an embodiment of the invention comprises a sequential series or plurality of FIFO buffers associated with read and write counters or pointers to indicate the next FIFO buffer in the sequential series from which data should be read, or to which data should be written. Read and write address decoders are coupled between the FIFO buffers and the read and write counters, respectively, to decode the pointer indicators to a particular FIFO buffer indicator. Of particular interest within the FIFO buffer system is the way in which the read counter operates. The read counter tracks both the current and previous setting for the read counter, yet indicates through the decoder to the FIFO buffers the previous setting as the particular buffer to which the read counter is pointing. A result of this form of operation is that the first read latch signal sent to the read counter is ignored so far as the read counter"" indicator is concerned. Following a reset signal, the read counter points to the first of the series of FIFO buffers even after receiving the first read latch signal. Subsequently, the pointer increments one buffer in the sequential series of FIFO buffers for each read latch signal received. Another result of this form of operation is that through the control logic associated with the FIFO buffer system, the write counter always points at least one FIFO buffer ahead of the FIFO buffer to which the read counter is pointing. This allows the FIFO system to read buffers while writing to other buffers.
In particular use with a dynamic random access memory (DRAM) device, the FIFO buffer system stores address commands until corresponding data to be stored arrives at the DRAM. This frees up the DRAM pipelines for use with transferring data rather than storing address commands for the data.
In one embodiment of the FIFO buffer system within a DRAM device, the read counter comprises a plurality of registers to track the current and previous register settings. A two to four decoder is used to decode a two digit binary code indicating the previous state into a signal to activate one of four decoder outputs corresponding to related FIFO buffers. For each decoder output activated, a column address buffer and a row address buffer are activated.
In another embodiment of the FIFO buffer system, the read counter comprises a linear feedback shift register to track both the current and previous register settings and indicate the previous register setting as the FIFO buffer to which the read counter is pointing.